1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to the optimized design and fabrication of memory device core cells.
2. Description of the Related Art
Semiconductor memory cores are typically laid-out in array format, such that each individual core cell is coupled by a wordline and a pair of differential bitlines. To read or write data from or to a selected core cell, associated memory accessing circuitry is commonly designed around a memory core. For example, several key memory access circuit components typically include addressing circuitry for selecting a core cell, wordline drivers for driving a selected wordline, sense amplifiers for amplifying the signals that are read from selected core cells and output buffers.
As computer manufactures continue to push for new limits in performance, memory devices will also be required to operate at improved performance levels. Therefore, both the design and the fabrication of memory devices should be fine tuned to eliminate known and expected delays and inefficiencies.
With this in mind, FIG. 1A shows a simplified diagram of a memory core 10 that has an array of core cells 12. Each of the core cells 12 are interconnected by a pair of bitlines, such as bitline (BL) 14 and a complimentary bitline (/BL) 16. Each core cell is also electrically interconnected with other core cells 12 along horizontal wordlines (WL) 18. As mentioned above, sense amplifying circuitry is usually implemented to read data, and write drivers to write data into selected core cells 12.
Although conventional sense amplifying circuitry has worked well in the past for sensing voltage differentials between the bitlines 14 and 16, higher performance memory devices are now requiring the ability to sense very small voltage differentials in the bitlines. By way of example, traditional sense amplifiers were previously required to sense voltage differentials of approximately 500 millivolts (mV) between the bitlines 14 and 16 in order to commence a reading of data that may be stored in a particular core cell 12. Due to expected fabrication imperfections and circuit layout constraints, there is usually a voltage offset between the bitlines 14 and 16. Commonly, voltage offsets are expected to be between about 5 to 30 millivolts.
Even though such offsets are expected and usual, these voltages offsets are quite insignificant compared to the 500 millivolt voltage differential required for triggering amplification by a sense amplifier. However, higher performance memory devices are now requiring that amplification by a sense amplifier occur at much faster rates and are therefore required to sense voltage differentials of between about 15 and 60 millivolts between the bitlines. Unfortunately, voltage offsets in the range of between about 5 and 30 millivolts will necessarily begin to hamper the speed at which sense amplification may occur.
FIG. 1B shows a pair of exemplary bitlines 14 and 16 that are interconnecting successive core cells 12 in the vertical column direction. Also shown are representative wordlines 18 that horizontally interconnect each of the core cells 12. As is well known, the core cells 12 are typically symmetric data latching circuits that have cross-coupled inverters and passgate transistors that are coupled to respective wordlines 18. Although the core cells 12 are symmetric in their schematic circuit representation, the resulting geometric shape and layout orientation on a semiconductor substrate will usually be less than perfectly symmetric.
As a result, the capacitive loading experienced on each of the respective bitlines 14 and 16 will not be equal. That is, when the voltage at point 32 is driven to a rail voltage (Vdd), capacitive coupling of C1 will occur between pre-charged transistors 30 and the bitlines 14 and 16. As pictorially shown in FIG. 1B, if the capacitive loading in the bitline 14 is xe2x80x9cC+xcex94Cxe2x80x9d and the capacitive loading in the complementary bitline 16 is xe2x80x9cC,xe2x80x9d then there will be a voltage offset of xcex94V between bitlines 14 and 16 due to miller coupling capacitance. In other words, bitline 14 may have a voltage of V, and the complimentary bitline 16 may have a voltage of V+xcex94V. It is this voltage offset that becomes problematic when voltage sensing between the bitlines is required at lower voltage differentials. This problem occurs while reading a low on complementary bitline 16, when the complementary bitline 16 has a voltage of V+xcex94V.
For example, FIG. 1C shows bitline 14 and the complimentary bitline 16 graphed in terms of voltage and time, and illustrating that sense application will occur when accessing data of a particular core cell 12. In this example, the voltage offset is shown to be 15 milli-volts (mV) between the bitline 14 and the complimentary bitline 16. When sensing of digital data that is stored in a particular core cell occurs, the complimentary bitline 16 will begin to fall at a time TO. Of course, the complimentary bitline 16 must first cross the bitline 14 at a time T1. Therefore, higher performance sense amplifiers that are required to detect about 30 millivolt differences between the bitlines, and also have voltage offsets of 15 milli-volts (mV), will not commence their amplification until a time T3.
As can be graphically appreciated, if there were no voltage offset between the bitlines as represented by a complimentary bitline 16xe2x80x2, a sense amplifier would be able to sense a voltage differential of 30 millivolts much more rapidly at a time T2. Consequently, even very small voltage offsets will have substantially increased performance deteriorating ramifications. Unfortunately, conventional memory device performance is limited by the expected fabrication imperfections and layout constraints that produce imbalances in capacitive loading of the bitlines of each core cell 12.
In addition to capacitive loading imbalances, several semiconductor layout constraints have prevented further miniaturization of the physical size of an individual core cell 12. Because traditional six transistor core cells have two cross-coupled inverters laid out in the center of a core cell, the gates of four transistors of the two cross-coupled inverters are formed from by interposing polysilicon lines. FIG. 1D shows the conventional layout of the polysilicon lines that form the gates of the four transistors in the two cross-coupled inverters.
Although this layout works well, the space needed to layout the polysilicon lines and complete the cross-coupling in polysilicon have severely limited the ability to reduce a core cell""s overall size. In this conventional design, a core cell 12 will typically have a height xe2x80x9cHxe2x80x9d of about 3.2 microns and a width xe2x80x9cWxe2x80x9d of about 5.4 microns in a 0.25 micron process. Because six transistor core cells require four transistors (i.e., two N-type transistors and two P-type transistors for the two inverters) in a cross-coupled arrangement, it is very difficult to further shrink the size of a standard core cell 12.
In view of the foregoing, what is needed is a method and apparatus for substantially eliminating voltage offsets along bitlines of a memory device, and for improving the speed at which sensing of small voltage differentials between memory bitlines can occur. There is also a need for more compact core cell layouts that enable the layout of more core cells in substantially less semiconductor surface area.
Broadly speaking, the present invention fills these needs by providing memory layout techniques that substantially eliminate voltage offsets between memory core cell bitlines, as well as techniques for laying out core cells in substantially less semiconductor chip area. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a method of designing a memory device that has reduced bitline voltage offsets is disclosed. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.
In yet another embodiment, a memory device having equalized bitline capacitive coupling is disclosed. The memory device includes a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The memory device further includes a six transistor core cell having a bitline and a complementary bitline, and a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. The multiple pairs of the global bitline and the global complementary bitline have a plurality of core cells that are defined by alternating ones of the six transistor core cell and the flipped six transistor core.
In still another embodiment, a system using a memory generator for making a memory device that has reduced bitline voltage offsets is disclosed. The system includes means for providing a memory core that has a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The system also includes means for designing a six transistor core cell having a bitline and a complementary bitline, and means for designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. The system further includes means for arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitlines and the global complementary bitlines.
In still yet a further embodiment, a memory core circuit design is disclosed. The circuit design has a polysilicon design that is routed over a semiconductor substrate. The polysilicon design is configured to define six gates of a six transistor core cell, and the six transistor core cell has four transistors that define two cross-coupled inverters. The crosscoupled inverters are electrically cross-coupled by a portion of the polysilicon design, a portion of a metallization line that is routed on a first metallization line, and a portion of a metallization line that is routed on a second metallization layer. Wherein the multi-layer electrical cross-coupling substantially reduces a physical size of the six transistor core cell.
Advantageously, the various embodiments of the present invention provide methods and apparatus for substantially eliminating voltage offsets between bitlines, and also provides techniques for designing very compact core cell layouts in multilevel semiconductor devices. As a further advantage, compact core cells have reduced line capacitance, which will necessarily improve performance. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.